The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating semiconductor gates.
As semiconductor devices scale down, gate leakage and polysilicon (poly) depletion have become critical issues.
U.S. Pat. No. 6,171,900 to Sun describes a method for fabricating a CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs (metal-oxide semiconductor field effect transistors).
U.S. Pat. No. 6,027,975 to Hergenrother et al. describes a process for fabricating a vertical MOSFET device for use in integrated circuits.
U.S. Pat. No. 4,115,914 to Harari describes a process for fabricating a nonvolatile field effect transistor in which an electrically floating gate acts as a charge storage medium.
U.S. Pat. No. 6,184,087 to Wu describes a method for fabricating a high speed and high density nonvolatile memory cell.
U.S. Pat. No. 5,304,503 to Yoon et al. describes a method for fabricating an EPROM (erasable programmable read only memory) cell array.
Accordingly, it is an object of an embodiment of the present invention to provide an improved method of fabricating a gate dielectric with reduced gate leakage.
Another object of an embodiment of the present invention is to provide an improved method of fabricating a gate electrode with reduced poly depletion.
A further object of an embodiment of the present invention is to provide a method to improve transistor performance.
Yet another object of an embodiment of the present invention is to provide a method of fabricating a high-k dielectric.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.